The position entails working with global Front-End design team and physical design team for large scale ASIC chip physical implementation; focusing on physical design of deep sub-micron GPU chips in the areas of floorplanning and timing closure of block level and full chip floor.
In this role, the selected candidate will participate in SOC full Chip DFT feature and architecture definition; implement SOC DFT functions including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
The candidate is required to drive the latest cutting edge technology development, look at metal layer definition, standard cell / ram design, vt selection/tuning, performance and area scaling from previous technology.
In this role, the selected candidate will promote, utilize and support quality assurance and quality control processes to improve the quality of deliverable and reduce design errors and omissions thereby resulting in a reduction in claims.
The successful candidate will assume ownership in development of firmware designed for an embedded u-controller; working with design and verification engineers to implement and verify all of the key features.
This position will be the point-of-contact between Manufacturing and the Program Management organization on projects or major project elements.In addition to the Program Management group, this position will work heavily with Quality Assurance, Business Management and Supply Chain Management.
In this role, the selected candidate must have knowledge with Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off will be helpful.
In this role, the selected candidate will be responsible for engaging on pre-silicon verification efforts, including but not limited to FPGA-based emulation, Design Verification (DV), and other software/hardware modeling frameworks.
The position includes characterization, data analysis, and yield debug of ATE and SLT manufacturing flows; applicant should be familiar with modern microprocessor manufacturing, semi-conductor device physics, testing techniques and failure mechanisms.
In this role, the selected candidate will build reusable test bench components such as test libraries, models, BFMs and checkers by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++.
In this role, the selected candidate will be responsible for developing Verification Components for Re-Usable Verification IP in SystemVerilog; writing, modifying, and maintaining random and directed Test Cases and Libraries.