In this role, you will selecting, designing and delivering a micro architecture, methodology, or other significant aspect of a high performance cpu core ip design with a high degree of independence.Analyzing multiple arch, uarch and circuit options to find the optimal design point considering power/performance/area/cost trade offs developing a functional block/unit rtl model then integrating and validating.
In this role, you will work will include design, simulated modeling, fabrication and experimental characterization of RF MEMS, ferroics ,and/or solid state hetero-structure devices at microwave frequencies.
In this role, the selected candidate creates step-by-step test documentation in parallel to collecting and organizing test data; identifies and escalates product risk areas from characterization tests and data analysis.
In this role, you will research into current state-of-the-art discrete rf/awg architectures used for qubits control- investigate minimum signal specifications, architectures and circuit design for rf/awg system for qubit control to be integrated in deeply-scaled cmos technologies and operate at very low-temperatures 10k.
In this role, the selected candidate will be responsible for all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
In this role, the selected candidate will assist in the development new test architectures and comprehensive test plans; work with R&D Engineering to gain direct experience with how customers use products.
In this role, the selected candidate will collaborate with team-members: firmware, software, mechanical engineers and PCB design specialists; work with procurement and production departments as your designs become products.
In this role, you will be responsible for
designing engineers to interpret schematics and drive physical implementation.Build and verify all levels of physical design hierarchy leaf cell, IP block, compiler.