In this role, you will deliver test masks, test patterns, sampling strategies, process models, defect detection strategies, and software algorithms to perform layout correction for one or more masks at the <=10 nm technology node.
In this role, the selected candidate will collaborate with team-members: firmware, software, mechanical engineers and PCB design specialists; work with procurement and production departments as your designs become products.
In this role, you will work will include design, simulated modeling, fabrication and experimental characterization of RF MEMS, ferroics ,and/or solid state hetero-structure devices at microwave frequencies.
In this role, you will be a part of the Corporate Memory Organization.You will drive physical implementation for a range of SRAM and Register File compiler designs across multiple process technology nodes.
In this role, you will be responsible for
analyzing multiple arch, uarch and circuit options to find the optimal design point considering power/performance/area/cost trade offs Developing a functional block/unit RTL model then integrating and validating.
In this role, you will selecting, designing and delivering a micro architecture, methodology, or other significant aspect of a high performance cpu core ip design with a high degree of independence.Analyzing multiple arch, uarch and circuit options to find the optimal design point considering power/performance/area/cost trade offs developing a functional block/unit rtl model then integrating and validating.
In this role, you will design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components.