In this role, you will understanding of entire physical design flow primetime sta tool and timing closure methodologies understanding of physical verification floor - planning the top level dieself-motivated and ability to work well within a team.
In this role, the selected candidate will lead or act as the chief technical contributor in the design of new applications or enhancements including integration of purchased solutions in accordance with Enterprise wide strategy.
This position is responsible for planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues.
In this role, you must have hands on experience with physical design and analysis tools in the areas of APR, parasitic extraction, physical verification, clock tree planning, timing analysis/optimization, padring design, IR/EM/coupling analysis.
In this role, you will work with the ip/soc architecture team to define the ip micro-architecture, develop/validate rtl and participate with the soc design, validation and emulation teams to ensure successful integration/validation of the ip.
In this role, the selected candidate uses multiple measures of student learning outcomes to formulate recommendations for course and program improvement. Presents research findings and recommendations to management and/or curriculum review committee as needed or requested.
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$50K to $83K -Phoenix, AZ
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