In this role, the selected candidate will be responsible for interpreting design inputs, executing custom pump designs on pro-engineer solids modeling tool, producing technical submittal documentation for customers and generating bills of material and detailed drawings for production.
In this role, the selected candidate will work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.
The Low Power Digital Synthesis Engineer will be responsible for all aspects of implementation including physical synthesis, constraints development, clock definitions, timing analysis, formal verification, low power flow (UPF), ECO flow, and working with the Physical Design team to optimize designs for power, area, and performance.
You will be responsible for design and development of IP and SOCs. This would include direct responsibility for digital SOC and IP development including architecture, microarchitecture, RTL, CDC, LINT, synthesis, STA, and LEC. - Technical oversight of deliverables to/from the verification, analog design, physical design, and DFT teams.
In this role, the selected candidate will work on design and verification methodology for various ASIC designs using multiple techniques (simulation, model checking, assertion-based verification, equivalence checking, and theorem proving).
The candidate will work hands on to develop new analysis and implementation methodologies and tools, and will work with the Qualcomm product testing, PD team, and synthesis teams to improve Qualcomms designs.
In this role, the selected candidate is responsible for the entire digital design flow from RTL to GDSII, including digital and mixed-signal circuits and systems that are integrated into integrated circuits (ICs), System-on-Chip (SoC) and complete chipsets that power Qualcomms wireless device portfolio.
The RF SiP Design Engineer will deliver Front-End Module designs in a fast-paced team environment, and is required to work closely with RF IC design engineers to optimize a design by extensive co-simulation and co-design based on RF system knowledge.