In this role, the selected candidate performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
In this role, the selected candidate will validate high performance, data center network switches and other network hardware solutions from pizza boxes to large chassis covering the application space from TOR to backbone.
In this position, you will plan the test environment to thoroughly test the functionality and performance of the SOC chips, quickly and efficiently debug, isolate, and report problems and issues that come up in the lab while testing or from customers.
In this highly visible role, as part of a highly talented team you will be at the heart of the chip design effort interfacing with all disciplines (vertical product model) with critical impact in getting functional products to millions of customers quickly.
In this role, the selected candidate must have a knowledge of FDA cGMP related regulations & guidelines and specific knowledge of computer validation methodologies and principles to perform CSV on a variety of systems and programs.
The primary role is to engage in power hardware validation and analysis of typical SoC workloads. The analysis of the workloads and their power dissipation will help drive the power optimization efforts to achieve best-in-class power/performance.
The ideal candidate should exhibit the following behavioral traits: - Problem-solving skills - Ability to multitask - Strong written and verbal communication skills - Ability to work in a dynamic and team oriented environment.
In this role, you will develop software solutions and flows per plan include tests to release/qualify Will be involved with Pre-Silicon tape-out debug tool validation sign-offs, Silicon Bring-ups and Silicon Testing and debug efforts.