You will be responsible for design and development of IP and SOCs. This would include direct responsibility for digital SOC and IP development including architecture, microarchitecture, RTL, CDC, LINT, synthesis, STA, and LEC. - Technical oversight of deliverables to/from the verification, analog design, physical design, and DFT teams.
This position reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of Technology nodes. Your role is focused on the development of Digital design enablement collateral to help GLOBALFOUNDRIES customers adopt the most advanced silicon technologies (14/10nm/7nm).
In this role, you will optimize and develop design architecture from chip inception through to the compliant net - list. The selected candidate will also be responsible for developing design constraints and Synthesis scripts.
In this role, the selected candidate will work closely with designers and engineers to define interface and user requirements; develop new approaches to complex interface and UX problems, and convey these designs in the form of presentations, prototypes, and design specifications.
In this role, you will understand customer specifications and how they relate to required hardware and firmware requirements. Define hardware and firmware requirements and then design, document and debug.
In this role, the selected candidate will be responsible for mobile devices, the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortune's list of "100 Best Companies to Work For". QCT is currently seeking digital design engineers for mixed-signal Power Management ASICs that support QCTs mobile platforms.
In this role, you will develop microcontroller based Application Specific Standard Products (ASSP). Activities include specification, planning, architecture, RTL and gate level design, logic synthesis, verification, test vector generation, and silicon validation. Evaluate and improve design flows and methodologies.
In this role, you will evaluate and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
In this role, you will work hands - on and own their design through the full ASIC development process from specification, RTL implementation, verification, synthesis timing closure, emulation and post silicon bring up.
In this role, the selected candidate will work closely with your peers, test engineers, field application engineers and product engineers to find the optimal and most cost efficient solution for our customers.