The successful execution and completion for portions of high end GPU Physical Design. As part of the Radeon Technology Group at AMD, be part of the team responsible for delivering the next generation of cutting edge graphics.
In this role, the selected candidate will be responsible for a new functional block of the complex 3D Graphics IP cores for a combined CPU/GPU development effort (APU and dGPU). RTL and DV skills are required.
In this role, the selected candidate will be responsible for researching and developing ideas and processes for new products as well as improving upon the performance and design of existing products and oversee production and packaging of that product.
In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. This team also is responsible for the Design and Verification of several critical as well as the integration to other subsystems and SoC.
In this role, the selected candidate will be able to build complex systems to meet various design requirements including (but not limited to) functionality, performance, power, area, scalability and testability.
In this role, the selected candidate will evaluate all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use; analyze equipment to establish operation data, conducts experimental tests, and evaluates results.
In this role, the selected candidate must have a knowledge with Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off will be helpful.
In this role, you will define end product dimensional and functional criteria as a basis for the product/component design process utilizing principles of engineering reliability and dimensional management.
The candidate would participate on a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system.
In this role, the selected candidate will must be an expert in Design Verification techniques and methodologies including UVM, OVM or VMM as well as Formality, Coverage-based Constrained-Random methodologies and Emulation.
In this role, you will work with leading edge technologies and alongside some of the brightest colleagues in the industry to develop advanced real-time software designed for a variety of applications and processors that include complex imagers, laser illuminators, remote I/O subsystems, range finders and trackers and custom lens controllers.
In this role, the selected candidate will develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications; perform RTL design integration, insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints.
In this role, the selected candidate will focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc.