In this job you will be responsible for designing and coding BIST structures, setting up synthesis and timing constraints, running synthesis, logic equivalence checkers, and other front end tools as required.
The role involves RTL performance analysis and microbenchmarking for the DRAM memory controller IP. The engineer will work closely with the architecture, design and modeling teams working on high-performance memory controller designs. He or she will drive microbenchmarking plans at the IP level, and support performance debug at the SOC level.
In this role, the successful candidate will convert subsystems into real-world final designs for integration into final product; work in a team environment to create and engineer digital design subsystems from concept through to tape-out.
In this role, you will have the opportunity to utilize your hands on experience in parasitic extraction to develop/define&refine extraction and simulation methodologies for transistor as well as gate level designs.