Design, Modeling and Simulation of silicon photonics active and passive devices and components such as modulators, detectors, waveguides, edge and top couplers, PSRs, heaters and supporting FETs and FEOL and BEOL passive elements within the general technology capability.
Ensure that designed layouts pass Design Rule Checks (DRC). Specified layouts will be primarily test structures rather than working circuitry. Close and frequent cooperation with development engineers will be required.
Lead the engagement with Technology Development, Process Integration, Patterning, Metrology, Photolithograhy, Characterization, Data Preparation, Design Services, and Mask House teams, to generate specifications for optical and electrical designs as well as an overall frame structure.
Creating and managing the design of UX artifacts--personas, user/process flows, wireframes, storyboards, functional requirements, and site maps--to effectively communicate interaction and design ideas.
Lead multi-disciplined PW/supplier/airframe teams to meet technical, development, and production requirements. Lead/Supporting trade studies, coordinating exchange of technical data and resolving design issues.
Responsible and accountable for the electrical technical planning, scheduling, cost analysis, risk analysis and successful execution of small to medium programs or major electrical subsystems of a larger program containing substantial electrical content.
The candidate is expected to interact with the UTRC Program Offices and United Technologies Corporation (UTC) business units to enhance existing programs in the area of design of electric motors and generators for a large range of UTC products.
This position will be responsible for ensuring that site specific installation drawings reflect project development proposals, value engineering opportunities, and adhere to the NEC and other applicable codes and standards.
Design, Modeling and Simulation of silicon photonics active and passive devices and components such as modulators, detectors, waveguides, edge and top couplers, PSRs, heaters and supporting FETs and FEOL and BEOL passive elements within the general technology capability
Develops Frames bordering internal or client supplied chip designs to support the generation of semiconductor testsite and product masks for Fab 8 (Malta, NY) & Fab 1 (Dresden, Germany) advanced technology development.
In this role, the selected candidate will participate in the direction of work assigned to project teams; ability to obtain/maintain security clearance.; ability to work and interface effectively as part of a team.